A phase-locked loop (PLL) is an electronic circuit which uses a feedback path to generate an output signal wherein a phase and in many cases also a frequency of the output signal is “locked” to a reference signal. In particular, by using frequency dividers in a feedback path, a PLL may be used to generate an output signal having a frequency which is a multiple of a reference frequency. This may for example be used in communication circuits or other electronic devices to generate a clock signal having a comparatively high frequency based on a reference signal like a crystal oscillator signal having a comparatively low frequency.
Various types of PLLs are used, for example analog PLLs, digital PLL with a digital phase detector or all digital PLLs where phase detector, filter and oscillator are digital components.
One of the main parts of such a digital PLL is a digitally controlled oscillator (DCO), sometimes also referred to as numerically controlled oscillator (NCO). A DCO converts a digital signal supplied thereto as a control signal to an output signal having a frequency determined by the control signal and a gain factor Kdco of the DCO. This gain factor is in many implementations significantly dependent on processor, voltage and temperature variations, commonly abbreviated PVT. High frequency PLLs (for example operating at frequencies in the Megahertz or Gigahertz range) produce electromagnetic fields which may cause problems by interfering with electronic devices or circuits close to the PLL. This phenomenon is referred to as electromagnetic interference, EMI. To reduce or avoid such electromagnetic interference, a peak output power of an output signal of the PLL is required to be below a certain predetermined limit. To achieve this, the output frequency of the PLL in some implementations is modulated, for example with a random sequence, thus broadening the output spectrum while reducing peak power. Such approaches are for example known under the term “spread spectrum clocking” (SSC). Such approaches reduce electromagnetic interference, but also increases a timing error or jitter of the signal generated by the PLL. If the jitter gets to large, e.g. in communication circuits this may lead for example to communication errors. Therefore, jitter needs to be below a certain limit. As explained above, the gain factor Kdco depends on PVT, which may lead to comparatively large jitter. Consequently, it is desirable to at least partially compensate the effects of PVT on digital PLL to reduce jitter.
One approach to compensate at least process variations is to measure a deviation caused by process variations during a production test and to store a compensation value in a register, which is then used to compensate the process variations. One drawback of this approach is that all the chips comprising such a PLL need to undergo this process, which consumes time during production test. Another disadvantage is that only process variations may be compensated, while temperature or voltage variations occurring during actual use are not compensated.
Another conventional approach is to measure a cross correlation between a random sequence and an output of a phase detector of the PLL, and use an on-off controller for compensation. An on-off controller increments or decrements a correction value in discrete steps depending on the above-mentioned correlation and one or more thresholds. In such an approach, instabilities of the controller may occur, and the controller needs a comparatively large chip area.
Further approaches using a correlation are disclosed in Nicola Da Dalt et al., “An All-Digital PLL Using Random Modulation for SSC Generation in 65 nm CMOS”, ISSCC 2013, IEEE International Solid-State Circuits Conference (Conference Proceedings), pages 252 ff.
It is an object to provide phase-locked loops where PVT variations may at least partially be compensated and which exhibit increased stability compared to conventional solutions.